The present disclosure relates to the field of semiconductor memory, and more particularly to methods and apparatuses for reducing power dissipation in a Static Random Access Memory (SRAM) device.
Referring to FIG. 1, a Static Random Access Memory (SRAM) device 100 is depicted. During a read operation, the SRAM device 100 is provided with an address decoder 104 for receiving an address and an internal clock signal (CLK_INT) generated by an internal clock generator 102. The internal clock generator 102 generates the internal clock signal using an external clock (CLK) and a Chip Selection Signal (CSN). The address decoder 104 decodes the address and generates a Word-Line (WL) signal to enable a WL. A WL driver 106 receives the WL signal from the address decoder 104 and transmits the WL signal to a SRAM Bit-Cell 108 which the WL signal enables the WL to select a Bit-Line (BL) in the SRAM Bit-Cell 108. The WL driver 106 is driven by a WL voltage (VDDWL) power supply switch 114. The WL voltage (VDDWL) power switch 114 is derived from the Chip Selection Signal (CSN) and a cell voltage supply (VDDCE).
Further, a tracking circuit 110 generates a Sense Amplifier Enable (SAE) signal and RESET signal using the internal clock signal generated by the internal clock generator 102. The tracking circuit 100 generates the SAE signal and RESET signal when WL selects the BL in the SRAM Bit-Cell 108. The SAE signal enables a Sense Amplifier 112 to perform a read operation by reading a data array of the SRAM Bit-Cell 108.
Referring to FIG. 2, during the read operation in the SRAM device 100, the WL selects at least one BL in the SRAM Bit-Cell 108. The tracking circuit 110 generates the SAE signal to enable the sense amplifier 112 to read the data of the array of the SRAM Bit-Cell 108, as mentioned in FIG. 1. When the sense amplifier 112 reads the data of the array of the SRAM Bit-Cell 108, the SRAM Bit-Cell 108 discharges power stored in the at least one selected BL and the power stored in the BLs which are unselected by the WL. The power discharging of the BLs is common during the read operation unless the power discharging of BLs exceeds a pre-defined voltage level required for the sense amplifier 112 to perform the read operation. As the power levels of the BLs are discharged, the current flow in the SRAM Bit-Cell 108 increases.
The power discharging of BLs may exceed a pre-defined voltage due to reasons such as: (i) When there is no change of state of the WL signal caused by a next read cycle and the WL is maintained in enabled state to make the current to flow through the SRAM Bit-Cell 108. (ii) Gate capacitance of a FINFET device (not shown) is more than a gate capacitance of a MOSFET device (not shown) in the SRAM device 100 such that a greater capacitance has to be charged/discharged.
In conventional methods and systems, the power discharging of the SRAM Bit-Cell 108 is reduced by disabling the WL completely for a short period of time using the address decoder 104 and the WL is again enabled during the next read cycle. However, disabling/enabling the WL for a particular period of time is time consuming during the read operation.